#include "processor.h"
#include "mmu.h"
-#include "sim.h"
#include <cassert>
{
commit_log_stash_privilege(p);
reg_t npc = fetch.func(p, fetch.insn, pc);
- if (!invalid_pc(npc)) {
+ if (npc != PC_SERIALIZE_BEFORE) {
commit_log_print_insn(p->get_state(), pc, fetch.insn);
p->update_histogram(pc);
}
if (unlikely(invalid_pc(pc))) { \
switch (pc) { \
case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
- case PC_SERIALIZE_AFTER: n = ++instret; break; \
+ case PC_SERIALIZE_AFTER: ++instret; break; \
+ case PC_SERIALIZE_WFI: n = ++instret; break; \
default: abort(); \
} \
pc = state.pc; \
{
while (instret < n)
{
+ if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
+ state.single_step = state.STEP_NONE;
+ if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+ enter_debug_mode(DCSR_CAUSE_STEP);
+ // enter_debug_mode changed state.pc, so we can't just continue.
+ break;
+ }
+ }
+
if (unlikely(state.single_step == state.STEP_STEPPING)) {
state.single_step = state.STEP_STEPPED;
}
if (debug && !state.serialized)
disasm(fetch.insn);
pc = execute_insn(this, pc, fetch);
- bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
advance_pc();
- if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
- state.single_step = state.STEP_NONE;
- enter_debug_mode(DCSR_CAUSE_STEP);
- // enter_debug_mode changed state.pc, so we can't just continue.
- break;
- }
-
if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
state.pc < DEBUG_END)) {
// We're waiting for the debugger to tell us something.