Support debug system bus access.

[riscv-isa-sim.git] / riscv / extension.h

diff --git a/riscv/extension.h b/riscv/extension.h
index 218deb4128df6f4ca60e128041ea02166e7e1387..d1e847d9b8ebff01511fbed25aef21f910313ac2 100644 (file)
--- a/riscv/extension.h
+++ b/riscv/extension.h
@@ -1,9 +1,10 @@
+// See LICENSE for license details.
+
 #ifndef _RISCV_COPROCESSOR_H
 #define _RISCV_COPROCESSOR_H
 
 #include "processor.h"
-#include <map>
-#include <string>
+#include "disasm.h"
 #include <vector>
 #include <functional>
 
@@ -11,7 +12,10 @@ class extension_t
 {
  public:
   virtual std::vector<insn_desc_t> get_instructions() = 0;
+  virtual std::vector<disasm_insn_t*> get_disasms() = 0;
   virtual const char* name() = 0;
+  virtual void reset() {};
+  virtual void set_debug(bool value) {};
   virtual ~extension_t();
 
   void set_processor(processor_t* _p) { p = _p; }
@@ -23,11 +27,12 @@ class extension_t
   void clear_interrupt();
 };
 
-std::map<std::string, std::function<extension_t*()>>& extensions();
+std::function<extension_t*()> find_extension(const char* name);
+void register_extension(const char* name, std::function<extension_t*()> f);
 
 #define REGISTER_EXTENSION(name, constructor) \
   class register_##name { \
-    public: register_##name() { extensions()[#name] = constructor; } \
+    public: register_##name() { register_extension(#name, constructor); } \
   }; static register_##name dummy_##name;
 
 #endif