Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / extensions.cc

diff --git a/riscv/extensions.cc b/riscv/extensions.cc
index 315621fd86fbbb93822bc00763b7eecc2670585e..d1690c4b8f65dd25159f84866b14fa132aac58c6 100644 (file)
--- a/riscv/extensions.cc
+++ b/riscv/extensions.cc
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 #include "extension.h"
 #include <string>
 #include <map>