client_fd(0),
recv_buf(64 * 1024), send_buf(64 * 1024)
{
- // TODO: listen on socket
socket_fd = socket(AF_INET, SOCK_STREAM, 0);
if (socket_fd == -1) {
fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
// Client can't take any more data right now.
break;
} else {
- printf("wrote %ld bytes: ", bytes);
+ fprintf(stderr, "wrote %ld bytes: ", bytes);
for (unsigned int i = 0; i < bytes; i++) {
- printf("%c", send_buf[i]);
+ fprintf(stderr, "%c", send_buf[i]);
}
- printf("\n");
+ fprintf(stderr, "\n");
send_buf.consume(bytes);
}
}
// "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
// "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
// "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
- // "pc",
- // "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- // "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- // "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- // "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
// Each byte of register data is described by two hex digits. The bytes with
// the register are transmitted in target byte order. The size of each
expect_ack = true;
}
+// First byte is the most-significant one.
+// Eg. "08675309" becomes 0x08675309.
uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
std::vector<uint8_t>::const_iterator end)
{
return value;
}
+// First byte is the least-significant one.
+// Eg. "08675309" becomes 0x09536708
+uint64_t consume_hex_number_le(std::vector<uint8_t>::const_iterator &iter,
+ std::vector<uint8_t>::const_iterator end)
+{
+ uint64_t value = 0;
+ unsigned int shift = 4;
+
+ while (iter != end) {
+ uint8_t c = *iter;
+ uint64_t c_value = character_hex_value(c);
+ if (c_value > 15)
+ break;
+ iter++;
+ value |= c_value << shift;
+ if ((shift % 8) == 0)
+ shift += 12;
+ else
+ shift -= 4;
+ }
+ return value;
+}
+
void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
std::vector<uint8_t>::const_iterator end, uint8_t separator)
{
}
}
+// gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
+// its source tree. We must interpret the numbers the same here.
+enum {
+ REG_XPR0 = 0,
+ REG_XPR31 = 31,
+ REG_PC = 32,
+ REG_FPR0 = 33,
+ REG_FPR31 = 64,
+ REG_CSR0 = 65,
+ REG_CSR4095 = 4160,
+ REG_END = 4161
+};
void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
{
// p n
- // Register order that gdb expects is:
- // "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
- // "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
- // "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
- // "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
- // "pc",
- // "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- // "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- // "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- // "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-
std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
unsigned int n = consume_hex_number(iter, packet.end());
if (*iter != '#')
processor_t *p = sim->get_core(0);
send("$");
running_checksum = 0;
- if (n < 32) {
- send(p->state.XPR[n]);
- } else if (n == 0x20) {
+
+ if (n >= REG_XPR0 && n <= REG_XPR31) {
+ send(p->state.XPR[n - REG_XPR0]);
+ } else if (n == REG_PC) {
send(p->state.pc);
+ } else if (n >= REG_FPR0 && n <= REG_FPR31) {
+ send(p->state.FPR[n - REG_FPR0]);
+ } else if (n >= REG_CSR0 && n <= REG_CSR4095) {
+ try {
+ send(p->get_csr(n - REG_CSR0));
+ } catch(trap_t& t) {
+ // It would be nicer to return an error here, but if you do that then gdb
+ // exits out of 'info registers all' as soon as it encounters a register
+ // that can't be read.
+ send((reg_t) 0);
+ }
} else {
- send("E02");
+ return send_packet("E02");
}
send_running_checksum();
expect_ack = true;
}
+void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
+{
+ // P n...=r...
+
+ std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
+ unsigned int n = consume_hex_number(iter, packet.end());
+ if (*iter != '=')
+ return send_packet("E05");
+ iter++;
+
+ reg_t value = consume_hex_number_le(iter, packet.end());
+ if (*iter != '#')
+ return send_packet("E06");
+
+ processor_t *p = sim->get_core(0);
+
+ if (n >= REG_XPR0 && n <= REG_XPR31) {
+ p->state.XPR.write(n - REG_XPR0, value);
+ } else if (n == REG_PC) {
+ p->state.pc = value;
+ } else if (n >= REG_FPR0 && n <= REG_FPR31) {
+ p->state.FPR.write(n - REG_FPR0, value);
+ } else if (n >= REG_CSR0 && n <= REG_CSR4095) {
+ try {
+ p->set_csr(n - REG_CSR0, value);
+ } catch(trap_t& t) {
+ return send_packet("EFF");
+ }
+ } else {
+ return send_packet("E07");
+ }
+
+ return send_packet("OK");
+}
+
void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
{
// m addr,length
instruction = mmu->load_uint32(address);
mmu->store_uint32(address, EBREAK);
}
- printf(">>> Read %x from %lx\n", instruction, address);
+ fprintf(stderr, ">>> Read %x from %lx\n", instruction, address);
}
void software_breakpoint_t::remove(mmu_t* mmu)
{
- printf(">>> write %x to %lx\n", instruction, address);
+ fprintf(stderr, ">>> write %x to %lx\n", instruction, address);
if (size == 2) {
mmu->store_uint16(address, instruction);
} else {
consume_string(feature, iter, packet.end(), ';');
if (iter != packet.end())
iter++;
- printf("is %s supported?\n", feature.c_str());
if (feature == "swbreak+") {
send("swbreak+;");
}
return send_running_checksum();
}
- printf("Unsupported query %s\n", name.c_str());
+ fprintf(stderr, "Unsupported query %s\n", name.c_str());
return send_packet("");
}
return handle_memory_binary_write(packet);
case 'p':
return handle_register_read(packet);
+ case 'P':
+ return handle_register_write(packet);
case 'c':
return handle_continue(packet);
case 's':
void gdbserver_t::handle()
{
- processor_t *p = sim->get_core(0);
- if (running && p->halted) {
- // The core was running, but now it's halted. Better tell gdb.
- switch (p->halt_reason) {
- case HR_NONE:
- fprintf(stderr, "Internal error. Processor halted without reason.\n");
- abort();
- case HR_STEPPED:
- case HR_INTERRUPT:
- case HR_CMDLINE:
- case HR_ATTACHED:
- // There's no gdb code for this.
- send_packet("T05");
- break;
- case HR_SWBP:
- send_packet("T05swbreak:;");
- break;
+ if (client_fd > 0) {
+ processor_t *p = sim->get_core(0);
+ if (running && p->halted) {
+ // The core was running, but now it's halted. Better tell gdb.
+ switch (p->halt_reason) {
+ case HR_NONE:
+ fprintf(stderr, "Internal error. Processor halted without reason.\n");
+ abort();
+ case HR_STEPPED:
+ case HR_INTERRUPT:
+ case HR_CMDLINE:
+ case HR_ATTACHED:
+ // There's no gdb code for this.
+ send_packet("T05");
+ break;
+ case HR_SWBP:
+ send_packet("T05swbreak:;");
+ break;
+ }
+ send_packet("T00");
+ // TODO: Actually include register values here
+ running = false;
}
- send_packet("T00");
- // TODO: Actually include register values here
- running = false;
- }
- if (client_fd > 0) {
this->read();
this->write();
projects / riscv-isa-sim.git / blobdiff