Implement register writes.

[riscv-isa-sim.git] / riscv / gdbserver.h

diff --git a/riscv/gdbserver.h b/riscv/gdbserver.h
index 8f52a92e9566a4ba9d151077ccc433753ebea82b..8a7111fbe6a6f7c9028f4b297886d01db67ce755 100644 (file)
--- a/riscv/gdbserver.h
+++ b/riscv/gdbserver.h
@@ -77,6 +77,7 @@ public:
   void handle_memory_read(const std::vector<uint8_t> &packet);
   void handle_query(const std::vector<uint8_t> &packet);
   void handle_register_read(const std::vector<uint8_t> &packet);
+  void handle_register_write(const std::vector<uint8_t> &packet);
   void handle_step(const std::vector<uint8_t> &packet);
 
 private: