Fix paddr_bits computation prior to VM setup

[riscv-isa-sim.git] / riscv / htif.cc

diff --git a/riscv/htif.cc b/riscv/htif.cc
index 4a462ecbdc8387723c548373b4f2d4c1db3b68e7..6e8fee9e462127e07f8ff8ac8ec962b3dd067974 100644 (file)
--- a/riscv/htif.cc
+++ b/riscv/htif.cc
@@ -66,7 +66,7 @@ void htif_isasim_t::tick_once()
         reg_t addr = (hdr.addr + i) * HTIF_DATA_ALIGN;
         try {
           sim->debug_mmu->store_uint64(addr, buf[i]);
-        } catch (trap_load_access_fault& e) {
+        } catch (trap_store_access_fault& e) {
           fprintf(stderr, "HTIF: attempt to write to illegal address 0x%" PRIx64 "\n", addr);
           exit(-1);
         }
@@ -86,13 +86,6 @@ void htif_isasim_t::tick_once()
       packet_header_t ack(HTIF_CMD_ACK, seqno, 1, 0);
       send(&ack, sizeof(ack));
 
-      if (coreid == 0xFFFFF) // system control register space
-      {
-        uint64_t scr = sim->get_scr(regno);
-        send(&scr, sizeof(scr));
-        break;
-      }
-
       processor_t* proc = sim->get_core(coreid);
       bool write = hdr.cmd == HTIF_CMD_WRITE_CONTROL_REG;
       if (write)
@@ -100,16 +93,6 @@ void htif_isasim_t::tick_once()
 
       switch (regno)
       {
-        case CSR_MTOHOST:
-          old_val = proc->get_state()->tohost;
-          if (write)
-            proc->get_state()->tohost = new_val;
-          break;
-        case CSR_MFROMHOST:
-          old_val = proc->get_state()->fromhost;
-          if (write && old_val == 0)
-            proc->set_csr(CSR_MFROMHOST, new_val);
-          break;
         case CSR_MRESET:
           old_val = !proc->running();
           if (write)