Fix paddr_bits computation prior to VM setup

[riscv-isa-sim.git] / riscv / htif.cc

diff --git a/riscv/htif.cc b/riscv/htif.cc
index c7ba8fca8a7a767314fc792915ab2cf4a9e87e70..6e8fee9e462127e07f8ff8ac8ec962b3dd067974 100644 (file)
--- a/riscv/htif.cc
+++ b/riscv/htif.cc
@@ -1,6 +1,9 @@
+// See LICENSE for license details.
+
 #include "htif.h"
-#include "common.h"
 #include "sim.h"
+#include "mmu.h"
+#include "encoding.h"
 #include <unistd.h>
 #include <stdexcept>
 #include <stdlib.h>
@@ -14,9 +17,14 @@ htif_isasim_t::htif_isasim_t(sim_t* _sim, const std::vector<std::string>& args)
 {
 }
 
-void htif_isasim_t::tick()
+bool htif_isasim_t::tick()
 {
+  if (done())
+    return false;
+
   do tick_once(); while (reset);
+
+  return true;
 }
 
 void htif_isasim_t::tick_once()
@@ -39,17 +47,30 @@ void htif_isasim_t::tick_once()
       send(&ack, sizeof(ack));
 
       uint64_t buf[hdr.data_size];
-      for (size_t i = 0; i < hdr.data_size; i++)
-        buf[i] = sim->mmu->load_uint64((hdr.addr+i)*HTIF_DATA_ALIGN);
+      for (size_t i = 0; i < hdr.data_size; i++) {
+        reg_t addr = (hdr.addr + i) * HTIF_DATA_ALIGN;
+        try {
+          buf[i] = sim->debug_mmu->load_uint64(addr);
+        } catch (trap_load_access_fault& e) {
+          fprintf(stderr, "HTIF: attempt to read from illegal address 0x%" PRIx64 "\n", addr);
+          exit(-1);
+        }
+      }
       send(buf, hdr.data_size * sizeof(buf[0]));
       break;
     }
     case HTIF_CMD_WRITE_MEM:
     {
       const uint64_t* buf = (const uint64_t*)p.get_payload();
-      for (size_t i = 0; i < hdr.data_size; i++)
-        sim->mmu->store_uint64((hdr.addr+i)*HTIF_DATA_ALIGN, buf[i]);
-
+      for (size_t i = 0; i < hdr.data_size; i++) {
+        reg_t addr = (hdr.addr + i) * HTIF_DATA_ALIGN;
+        try {
+          sim->debug_mmu->store_uint64(addr, buf[i]);
+        } catch (trap_store_access_fault& e) {
+          fprintf(stderr, "HTIF: attempt to write to illegal address 0x%" PRIx64 "\n", addr);
+          exit(-1);
+        }
+      }
       packet_header_t ack(HTIF_CMD_ACK, seqno, 0, 0);
       send(&ack, sizeof(ack));
       break;
@@ -57,41 +78,34 @@ void htif_isasim_t::tick_once()
     case HTIF_CMD_READ_CONTROL_REG:
     case HTIF_CMD_WRITE_CONTROL_REG:
     {
+      assert(hdr.data_size == 1);
       reg_t coreid = hdr.addr >> 20;
       reg_t regno = hdr.addr & ((1<<20)-1);
-      assert(hdr.data_size == 1);
+      uint64_t old_val, new_val = 0 /* shut up gcc */;
 
       packet_header_t ack(HTIF_CMD_ACK, seqno, 1, 0);
       send(&ack, sizeof(ack));
 
-      if (coreid == 0xFFFFF) // system control register space
-      {
-        uint64_t pcr = sim->get_scr(regno);
-        send(&pcr, sizeof(pcr));
-        break;
-      }
-
-      assert(coreid < sim->num_cores());
-      uint64_t pcr = sim->procs[coreid]->get_pcr(regno);
-      send(&pcr, sizeof(pcr));
+      processor_t* proc = sim->get_core(coreid);
+      bool write = hdr.cmd == HTIF_CMD_WRITE_CONTROL_REG;
+      if (write)
+        memcpy(&new_val, p.get_payload(), sizeof(new_val));
 
-      if (regno == PCR_TOHOST)
-          sim->procs[coreid]->tohost = 0;
-
-      if (hdr.cmd == HTIF_CMD_WRITE_CONTROL_REG)
+      switch (regno)
       {
-        uint64_t val;
-        memcpy(&val, p.get_payload(), sizeof(val));
-        if (regno == PCR_RESET)
-        {
-          reset = val & 1;
-          sim->procs[coreid]->reset(reset);
-        }
-        else
-        {
-          sim->procs[coreid]->set_pcr(regno, val);
-        }
+        case CSR_MRESET:
+          old_val = !proc->running();
+          if (write)
+          {
+            reset = reset & (new_val & 1);
+            proc->reset(new_val & 1);
+          }
+          break;
+        default:
+          abort();
       }
+
+      send(&old_val, sizeof(old_val));
       break;
     }
     default:
@@ -100,8 +114,9 @@ void htif_isasim_t::tick_once()
   seqno++;
 }
 
-void htif_isasim_t::stop()
+bool htif_isasim_t::done()
 {
-  htif_t::stop();
-  exit(exit_code());
+  if (reset)
+    return false;
+  return !sim->running();
 }