add BSD license

[riscv-isa-sim.git] / riscv / htif.h

diff --git a/riscv/htif.h b/riscv/htif.h
index d7a8c898197db39e9bb39304ef130e8e7389fc6a..3e4a88dc6a1ca1af495221ea075c4169bcff2887 100644 (file)
--- a/riscv/htif.h
+++ b/riscv/htif.h
@@ -1,36 +1,31 @@
+// See LICENSE for license details.
+
 #ifndef _HTIF_H
 #define _HTIF_H
 
-#include <stdint.h>
+#include <fesvr/htif_pthread.h>
 
 class sim_t;
 struct packet;
 
 // this class implements the host-target interface for program loading, etc.
-class htif_t
+// a simpler implementation would implement the high-level interface
+// (read/write cr, read/write chunk) directly, but we implement the lower-
+// level serialized interface to be more similar to real target machines.
+
+class htif_isasim_t : public htif_pthread_t
 {
 public:
-  htif_t(int _tohost_fd, int _fromhost_fd);
-  ~htif_t();
-  void init(sim_t* _sim);
-
-  // wait for host to send start command
-  void wait_for_start();
-
-  // we block on the host if the target machine reads the fromhost register,
-  // which provides determinism in tohost/fromhost communication.
-  void wait_for_tohost_write();
-  void wait_for_fromhost_write();
+  htif_isasim_t(sim_t* _sim, const std::vector<std::string>& args);
+  void tick();
+  bool done();
 
 private:
   sim_t* sim;
-  int tohost_fd;
-  int fromhost_fd;
-  uint16_t seqno;
+  bool reset;
+  uint8_t seqno;
 
-  void nack(uint16_t seqno);
-  void send_packet(packet* p);
-  int wait_for_packet();
+  void tick_once();
 };
 
 #endif