Set tval to 0 on traps with no specified tval

[riscv-isa-sim.git] / riscv / insn_template.cc

diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
index 5bd986e18be53d49e501b8d6d2275acc9aa51bd1..1e79326c462446a94f6a16aa2b0cf7384ef45d16 100644 (file)
--- a/riscv/insn_template.cc
+++ b/riscv/insn_template.cc
@@ -1,25 +1,21 @@
 // See LICENSE for license details.
 
-#include "processor.h"
-#include "config.h"
-#include "mmu.h"
-#include "softfloat.h"
-#include "platform.h" // softfloat isNaNF32UI, etc.
-#include "internals.h" // ditto
-#include <assert.h>
+#include "insn_template.h"
 
-reg_t processor_t::rv32_NAME(insn_t insn, reg_t pc)
+reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
-  int xprlen = 32;
-  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  int xlen = 32;
+  reg_t npc = sext_xlen(pc + insn_length(OPCODE));
   #include "insns/NAME.h"
+  trace_opcode(p, OPCODE, insn);
   return npc;
 }
 
-reg_t processor_t::rv64_NAME(insn_t insn, reg_t pc)
+reg_t rv64_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
-  int xprlen = 64;
-  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  int xlen = 64;
+  reg_t npc = sext_xlen(pc + insn_length(OPCODE));
   #include "insns/NAME.h"
+  trace_opcode(p, OPCODE, insn);
   return npc;
 }