reorganise twin-predication

[riscv-isa-sim.git] / riscv / insn_template_sv.cc

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 7e9846296c097f58b2e22f42a8fe25a9fb27e516..cab74d7c8f9ea254589f58183eec7050bb6b45e1 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -19,13 +19,27 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   // REGS_PATTERN is generated by id_regs.py (per opcode)
   unsigned int floatintmap = REGS_PATTERN;
   reg_t dest_pred = ~0x0;
-  sv_insn_t insn(p, bits, floatintmap,
-                 dest_pred, dest_pred, dest_pred, dest_pred);
-  bool zeroing;
-#if defined(USING_REG_RD) || defined(USING_REG_FRD)
+  int dest_offs = 0;
+  bool zeroing = false;
+#ifdef INSN_CATEGORY_TWINPREDICATION
+  reg_t src_pred = ~0x0;
+  int src_offs = 0;
+  bool zeroingsrc = false;
+#endif
+  sv_insn_t insn(p, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
+  if (vlen > 0)
+  {
+    fprintf(stderr, "pre-ex reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
+            xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
+            vlen);
+#ifdef INSN_CATEGORY_TWINPREDICATION
+    src_pred = insn.predicate(s_insn.SRC_REG(), SRC_PREDINT, zeroingsrc);
+#endif
+#ifdef DEST_PREDINT
   // use the ORIGINAL, i.e. NON-REDIRECTED, register here
-  dest_pred = insn.predicate(s_insn.rd(), floatintmap & REG_RD, zeroing);
+    dest_pred = insn.predicate(s_insn.DEST_REG(), DEST_PREDINT, zeroing);
 #endif
+  }
   // identify which regs have had their CSR entries set as vectorised.
   // really could do with a macro for-loop here... oh well...
   // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
@@ -43,14 +57,60 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   }
   for (int voffs=0; voffs < vlen; voffs++)
   {
-      insn.reset_vloop_check();
+    insn.reset_vloop_check();
+#ifdef INSN_CATEGORY_TWINPREDICATION
+    if (src_offs >= vlen) {
+        break;
+    }
+    if (dest_offs >= vlen) {
+        break;
+    }
+#ifdef INSN_C_MV
+        fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
+            xstr(INSN), src_offs, dest_offs, src_pred, dest_pred);
+#endif
+    if (!zeroingsrc)
+    {
+      while ((src_pred & (1<<src_offs)) == 0) {
+          src_offs += 1;
+          if (src_offs >= vlen) {
+              break;
+          }
+      }
+    }
+    if (!zeroing)
+    {
+      while ((dest_pred & (1<<dest_offs)) == 0) {
+          dest_offs += 1;
+          if (dest_offs >= vlen) {
+              break;
+          }
+      }
+    }
+    if (src_offs >= vlen || dest_offs >= vlen) {
+        break; // end vector loop if either src or dest pred reaches end
+    }
+    if (vlen > 1)
+    {
+        fprintf(stderr, "twin reg %s src %d dest %d pred %lx %lx\n",
+            xstr(INSN), src_offs, dest_offs, src_pred, dest_pred);
+    }
+#endif
+#ifdef INSN_C_MV
+    fprintf(stderr, "pre loop reg %s %x vloop %d %d %d" \
+                      "vlen %d stop %d pred %lx rdv %lx rd %d rvc2 %d\n",
+                xstr(INSN), INSNCODE, voffs, src_offs, dest_offs,
+                vlen, insn.stop_vloop(),
+                dest_pred & (1<<voffs), READ_REG(insn._rd()),
+                insn._rd(), insn._rvc_rs2());
+#endif
       #include INCLUDEFILE
-#if defined(USING_REG_RD) || defined(USING_REG_FRD)
+#ifdef DEST_PREDINT
       // don't check inversion here as dest_pred has already been inverted
-      if (zeroing && ((dest_pred & (1<<voffs)) == 0))
+      if (zeroing && ((dest_pred & (1<<dest_offs)) == 0))
       {
           // insn._rd() would be predicated: have to use insn._rd() here
-          WRITE_REG(insn._rd(), 0);
+          WRITE_REG(insn._DEST_REG(), 0);
       }
 #endif
       if (vlen > 1)
@@ -63,14 +123,18 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #if defined(USING_REG_FRD)
         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_FREG(insn._rd()));
+                dest_pred & (1<<voffs),
+                (READ_FREG(insn._rd())));
 #endif
       }
-      insn.reset_caches(); // ready to increment offsets in next iteration
       if (insn.stop_vloop())
       {
         break;
       }
+#ifdef INSN_CATEGORY_TWINPREDICATION
+      src_offs += 1;
+#endif
+      dest_offs += 1;
   }
 #else
   insn_t insn(bits);