Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / add.h

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index 34d49ff31b932d4f48904e08336e2745ea8560e5..d7a5c98d21867debe16657aad778d6b1be191c7e 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + RS2);
+WRITE_RD(sext_xprlen(RS1 + RS2));