[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / addi.h

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index b6b208dc7af74fec1be93eba21b026555a0b2cf1..88881e5aec6561853fed1c45fec349deae6a6e57 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1,2 +1 @@
-require64;
-RA = SIMM + RB;
+RD = sext_xprlen(RS1 + SIMM);