[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / addi.h

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index b6b208dc7af74fec1be93eba21b026555a0b2cf1..e813eaec63c261b756638a92eb0510e7aa2a7e4a 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1,2 +1,2 @@
 require64;
-RA = SIMM + RB;
+RDI = SIMM + RS1;