[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / addiw.h

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 6935ccadea8c0c76ce4f2cdff22232ef7e1631ae..23ae2788407d8721196b69b284e845a62f04ef0d 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1 +1,2 @@
-RA = sext32(SIMM + RB);
+require_xpr64;
+RD = sext32(SIMM + RS1);