[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / addiw.h

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 6935ccadea8c0c76ce4f2cdff22232ef7e1631ae..6dfe5b1fab5643d3c8d3648e6234d3b2a03c9e00 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1 +1 @@
-RA = sext32(SIMM + RB);
+RDI = sext32(SIMM + RS1);