Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / addiw.h

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index a0608ed989946e3e48fd60954c4e9355e01b84fa..71ab2923e7b5015a8aec2741c8516d5cf1c13652 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(insn.i_imm() + RS1);
+WRITE_RD(sext32(insn.i_imm() + RS1));