[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / addw.h

diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index bfbc48568ddbf707f67c57f718022f31b370199c..4e2ed561677827fb72ffe7753d2d16823b88f017 100644 (file)
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
-RC = sext32(RA + RB);
-
+require_xpr64;
+RD = sext32(RS1 + RS2);