[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / addw.h

diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index f8715e36c46ffcc90de48217ed358ffa67e14561..4e2ed561677827fb72ffe7753d2d16823b88f017 100644 (file)
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
+require_xpr64;
 RD = sext32(RS1 + RS2);
-