[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amo_min.h

diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h
index 823550479ee91b3680cf412ab5938612ecbed8e1..7244e87d4ee8a84f66344d99cc30f742d6113014 100644 (file)
--- a/riscv/insns/amo_min.h
+++ b/riscv/insns/amo_min.h
@@ -1,4 +1,4 @@
 require64;
-sreg_t v = mmu.load_int64(RB);
-mmu.store_uint64(RB, std::min(sreg_t(RA),v));
-RC = v;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
+RDR = v;