[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amo_minu.h

diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h
index 0b617a10fd72bb9a956e3c7533756102d647bfba..3e365ab4a87153d92dbcbc2a8ca207ed2390e664 100644 (file)
--- a/riscv/insns/amo_minu.h
+++ b/riscv/insns/amo_minu.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, std::min(RA,v));
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::min(RS2,v));
+RDR = v;