[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amo_or.h

diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h
index 790a98caa49c9128c1d2e21e353b880cc20683ed..e7d81a8cd0d43ae3398ae1d4c6a0194a7c7c488e 100644 (file)
--- a/riscv/insns/amo_or.h
+++ b/riscv/insns/amo_or.h
@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA | v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 | v);
+RDR = v;