[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amow_add.h

diff --git a/riscv/insns/amow_add.h b/riscv/insns/amow_add.h
index fbf475d58e8e9dac60b11d9cfd1e3be0be66dae9..a55ddf9a3ad7e32678d00fc0b358710b61aea642 100644 (file)
--- a/riscv/insns/amow_add.h
+++ b/riscv/insns/amow_add.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA + v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 + v);
+RDR = v;