[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amow_and.h

diff --git a/riscv/insns/amow_and.h b/riscv/insns/amow_and.h
index 1166e8673668dc34d8c099358bd11800bb5f724c..f1670bde03a2ce28549e665b5c63b2e23434793d 100644 (file)
--- a/riscv/insns/amow_and.h
+++ b/riscv/insns/amow_and.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA & v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 & v);
+RDR = v;