[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amow_swap.h

diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amow_swap.h
index 6aec206a1ed30812ed34abccc92d53693d44b5c7..c8b108a114e1decdbd235ec4b6234d1fdbab8cd3 100644 (file)
--- a/riscv/insns/amow_swap.h
+++ b/riscv/insns/amow_swap.h
@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2);
+RDR = v;