[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / and.h

diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index 305e5417c384bde680a9307df209a2c1ef907438..a63e83f5feb35ea8755d7e80489b186366c464a5 100644 (file)
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RC = RA & RB;
+RDR = RS1 & RS2;