New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_add.h

diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
index 2170d69d632fc0421facd6e5b1c22d236e3816a2..64bc5f7578cc701393dd1f711a0a06583f708850 100644 (file)
--- a/riscv/insns/c_add.h
+++ b/riscv/insns/c_add.h
@@ -1,2 +1,7 @@
-require_rvc;
-CRD = CRS1 + CRS2;
+require_extension('C');
+require(insn.rvc_rs2() != 0);
+if (insn.rvc_rd() == 0) { // c.ebreak
+  throw trap_breakpoint();
+} else {
+  WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
+}