Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_add.h

diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
index c349fc022976fedea123efd6275be767a0e7c966..c13385ec4dec0bf471daaeb64f6bdb15b07bfcbf 100644 (file)
--- a/riscv/insns/c_add.h
+++ b/riscv/insns/c_add.h
@@ -1,2 +1,12 @@
 require_extension('C');
-WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
+if (insn.rvc_rs2() == 0) {
+  if (insn.rvc_rs1() == 0) { // c.ebreak
+    throw trap_breakpoint();
+  } else { // c.jalr
+    reg_t tmp = npc;
+    set_pc(RVC_RS1 & ~reg_t(1));
+    WRITE_REG(X_RA, tmp);
+  }
+} else {
+  WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
+}