New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_addi.h

diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
index 762f5c2fe144b70b3b4a68a2d134e3b6d27586b0..cea2a1812e3fe8aaa2729489e153864cb40951f6 100644 (file)
--- a/riscv/insns/c_addi.h
+++ b/riscv/insns/c_addi.h
@@ -1,2 +1,7 @@
-require_rvc;
-WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_imm()));
+require_extension('C');
+if (insn.rvc_rd() == 0) { // c.addi16sp
+  WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
+} else {
+  require(insn.rvc_imm() != 0);
+  WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm()));
+}