Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_addi.h

diff --git a/riscv/insns/c_addi.h b/riscv/insns/c_addi.h
index cea2a1812e3fe8aaa2729489e153864cb40951f6..eb983442a37e1407e1eb2240737a5ab76f7820ae 100644 (file)
--- a/riscv/insns/c_addi.h
+++ b/riscv/insns/c_addi.h
@@ -1,7 +1,2 @@
 require_extension('C');
-if (insn.rvc_rd() == 0) { // c.addi16sp
-  WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
-} else {
-  require(insn.rvc_imm() != 0);
-  WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm()));
-}
+WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm()));