Improve instruction fetch

[riscv-isa-sim.git] / riscv / insns / c_addiw.h

diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
index fe87872b42251964fec846cdf52f46ae9c627edf..05d349713fed39ddd5c4b2356944d8b92f7624e5 100644 (file)
--- a/riscv/insns/c_addiw.h
+++ b/riscv/insns/c_addiw.h
@@ -1,2 +1,3 @@
 require_extension('C');
+require_rv64;
 WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));