clean up shift instruction implementation

[riscv-isa-sim.git] / riscv / insns / c_addiw.h

diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
index 6a1e0a3cbce1a0962b219b6c605a376a263e4243..05d349713fed39ddd5c4b2356944d8b92f7624e5 100644 (file)
--- a/riscv/insns/c_addiw.h
+++ b/riscv/insns/c_addiw.h
@@ -1,3 +1,3 @@
-require_rvc;
-require_xpr64;
-CRD = sext32(CRS2 + CIMM6);
+require_extension('C');
+require_rv64;
+WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));