New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_addiw.h

diff --git a/riscv/insns/c_addiw.h b/riscv/insns/c_addiw.h
index 33f970c271fcbbf03fa9aaac689794ab319b2ba9..27ffd8f52bfba5f9bbddf203f7b182f80bfea63a 100644 (file)
--- a/riscv/insns/c_addiw.h
+++ b/riscv/insns/c_addiw.h
@@ -1,3 +1,4 @@
-require_rvc;
+require_extension('C');
 require_rv64;
-WRITE_RD(sext32(RVC_RS2 + insn.rvc_imm()));
+require(insn.rvc_rd() != 0);
+WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));