Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_addw.h

diff --git a/riscv/insns/c_addw.h b/riscv/insns/c_addw.h
index 36559b707dbfc1ad964414a0879c10939b0d54fd..fef554d1f62ed7cce7e27b7ad5c2f220e667c98c 100644 (file)
--- a/riscv/insns/c_addw.h
+++ b/riscv/insns/c_addw.h
@@ -1,4 +1,3 @@
 require_extension('C');
 require_rv64;
-require(insn.rvc_rd() != 0 && insn.rvc_rs2() != 0);
 WRITE_RD(sext32(RVC_RS1 + RVC_RS2));