New RV64C proposal
[riscv-isa-sim.git] / riscv / insns / c_ld.h
index 37b0ee2c630dd3f1e672f70f34427b4349f1d28b..876baddd056cd528f1af7a5354cce7de8288036a 100644 (file)
@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
-WRITE_RVC_RDS(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
+WRITE_RVC_RS2S(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));