Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_lui.h

diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index 040d7ecb4af31f2cc305b75958b5deb036735f5a..cb76c61a52020b03e572b9c3fec9ffc9d94542f3 100644 (file)
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -1,9 +1,6 @@
 require_extension('C');
-require(insn.rvc_rd() != 0);
-if (insn.rvc_imm() == 0) { // c.jalr
-  reg_t tmp = npc;
-  set_pc(RVC_RS1 & ~reg_t(1));
-  WRITE_REG(X_RA, tmp);
+if (insn.rvc_rd() == 0) { // c.addi16sp
+  WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
 } else {
   WRITE_RD(insn.rvc_imm() << 12);
 }