Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_lui.h

diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index 4bd4f87de91f034268cec9870dae326f48273e0a..cb76c61a52020b03e572b9c3fec9ffc9d94542f3 100644 (file)
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -1,2 +1,6 @@
 require_extension('C');
-WRITE_RD(insn.rvc_imm() << 12);
+if (insn.rvc_rd() == 0) { // c.addi16sp
+  WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
+} else {
+  WRITE_RD(insn.rvc_imm() << 12);
+}