Improve instruction fetch

[riscv-isa-sim.git] / riscv / insns / c_lui.h

diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h
index cb76c61a52020b03e572b9c3fec9ffc9d94542f3..e5060a37892ab6fbb184de2819d25d9b48fb2a98 100644 (file)
--- a/riscv/insns/c_lui.h
+++ b/riscv/insns/c_lui.h
@@ -1,6 +1,3 @@
 require_extension('C');
-if (insn.rvc_rd() == 0) { // c.addi16sp
-  WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
-} else {
-  WRITE_RD(insn.rvc_imm() << 12);
-}
+require(insn.rvc_rd() != 0);
+WRITE_RD(insn.rvc_imm() << 12);