Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_mv.h

diff --git a/riscv/insns/c_mv.h b/riscv/insns/c_mv.h
index df5cea6c260c038e3c67cf6e9a68dfe641c7fc0c..4a23063741c03e119a49916713102d27249dd387 100644 (file)
--- a/riscv/insns/c_mv.h
+++ b/riscv/insns/c_mv.h
@@ -1,3 +1,7 @@
 require_extension('C');
-require(insn.rvc_rd() != 0);
-WRITE_RD(RVC_RS2);
+if (insn.rvc_rs2() == 0) {
+  require(insn.rvc_rd() != 0);
+  set_pc(RVC_RS1 & ~reg_t(1));
+} else {
+  WRITE_RD(RVC_RS2);
+}