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[riscv-isa-sim.git] / riscv / insns / c_sdsp.h

diff --git a/riscv/insns/c_sdsp.h b/riscv/insns/c_sdsp.h
index 6028b0fbf73f8904016081697268b0ce5e6882d4..db504ec40cd9bd34d94d988ede92941a1bf2212f 100644 (file)
--- a/riscv/insns/c_sdsp.h
+++ b/riscv/insns/c_sdsp.h
@@ -1,3 +1,7 @@
-require_rvc;
-require_rv64;
-MMU.store_uint64(RVC_SP + insn.rvc_ldsp_imm(), RVC_RS2);
+require_extension('C');
+if (xlen == 32) {
+  if (sreg_t(RVC_RS1S) < 0) // c.bltz
+    set_pc(pc + insn.rvc_b_imm());
+} else {
+  MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
+}