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[riscv-isa-sim.git] / riscv / insns / c_slliw.h

diff --git a/riscv/insns/c_slliw.h b/riscv/insns/c_slliw.h
index 87a59010a78d259a163ef0d5a509bdb9b5de12f2..643bf7445c8da09520f582d7e16caf3e50138a1c 100644 (file)
--- a/riscv/insns/c_slliw.h
+++ b/riscv/insns/c_slliw.h
@@ -1,5 +1,13 @@
 require_extension('C');
-require_rv64;
-require(insn.rvc_rd() != 0);
-require(insn.rvc_imm() < 32);
-WRITE_RD(sext32(RVC_RS1 << insn.rvc_imm()));
+if (xlen == 32) {
+  switch ((insn.bits() >> 5) & 3) {
+    case 0: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S + insn.rvc_simm3())); // c.addin
+    case 1: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S ^ insn.rvc_simm3())); // c.xorin
+    case 2: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S | insn.rvc_simm3())); // c.orin
+    case 3: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S & insn.rvc_simm3())); // c.andin
+  }
+} else {
+  require(insn.rvc_rd() != 0);
+  require(insn.rvc_imm() < 32);
+  WRITE_RD(sext32(RVC_RS1 << insn.rvc_imm()));
+}