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New RV64C proposal
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_swsp.h
diff --git
a/riscv/insns/c_swsp.h
b/riscv/insns/c_swsp.h
index 0508f120ba6dc1ace170e27a31f965a252774631..b8995ab05fd0596626e8c6a5d1770fc45cbd67d9 100644
(file)
--- a/
riscv/insns/c_swsp.h
+++ b/
riscv/insns/c_swsp.h
@@
-1,2
+1,2
@@
-require_
rvc
;
-
mmu.store_uint32(XPR[30]+CIMM6*4, C
RS2);
+require_
extension('C')
;
+
MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_
RS2);