Implement clearing-misa.C-while-PC-is-misaligned proposal

[riscv-isa-sim.git] / riscv / insns / csrrs.h

diff --git a/riscv/insns/csrrs.h b/riscv/insns/csrrs.h
index ec61b420a6b1c3420441f4c58226aefee9131acf..4e8bde96379935755ef87b32903e5aadd81a5227 100644 (file)
--- a/riscv/insns/csrrs.h
+++ b/riscv/insns/csrrs.h
@@ -5,3 +5,4 @@ if (write) {
   p->set_csr(csr, old | RS1);
 }
 WRITE_RD(sext_xlen(old));
+serialize();