Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH

[riscv-isa-sim.git] / riscv / insns / csrrw.h

diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 4b16773d6cbc02dce6c20756412b322f4c983157..94793e2911879b020477f725a99af7db31ff3c30 100644 (file)
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, RS1));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, RS1)));