Implement timer faithfully

[riscv-isa-sim.git] / riscv / insns / csrrwi.h

diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index b8ec5f5f90d6c7797908c1fe28ea9e83ed478edf..081b4e9573b4c139810b7ce9f7ad0c7d12be5521 100644 (file)
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,4 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(sext_xprlen(p->set_pcr(csr, insn.rs1())));
+reg_t old = p->get_pcr(csr);
+p->set_pcr(csr, insn.rs1());
+WRITE_RD(sext_xprlen(old));