Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH

[riscv-isa-sim.git] / riscv / insns / csrrwi.h

diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index ff20833782b59476502db4dae0c7f051222e1d4d..b8ec5f5f90d6c7797908c1fe28ea9e83ed478edf 100644 (file)
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,2 @@
 int csr = validate_csr(insn.csr(), true);
-WRITE_RD(p->set_pcr(csr, insn.rs1()));
+WRITE_RD(sext_xprlen(p->set_pcr(csr, insn.rs1())));