New RDCYCLE encoding

[riscv-isa-sim.git] / riscv / insns / csrrwi.h

diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index 840150e01ae18ca953708134db14131559661a8d..ff20833782b59476502db4dae0c7f051222e1d4d 100644 (file)
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -1,2 +1,2 @@
-int csr = validate_csr(insn.i_imm(), true);
+int csr = validate_csr(insn.csr(), true);
 WRITE_RD(p->set_pcr(csr, insn.rs1()));