[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / cvt_s_w.h

diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index 5bbe61f172ce06c378e6454336fa1ce385a17037..9db538636f045477a43354984739cb6a3a7802d4 100644 (file)
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = i32_to_f32(FRA);
+FRDR = i32_to_f32(FRS1);
 set_fp_exceptions;