[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / cvtu_s_w.h

diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index 8eaeca3d8f2df691203132f0c32d48f5da3cb3c0..252e0cc010fba887dc0aff86ef306fd33c9a6055 100644 (file)
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = ui32_to_f32(FRA);
+FRDR = ui32_to_f32(FRS1);
 set_fp_exceptions;