[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / di.h

diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index f555c2c479260309cf016edc41186d02e4d13b51..0f3adf9c8adce2660a8520e1bc099a7db863e6e9 100644 (file)
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RC = temp;
+RDR = temp;