[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / div_d.h

diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
index 884effcbcef48c10bbdda0b17ad10041ef3a9b31..9902da6e4d2f2b84ff5492ba56d6c06a290ff4e7 100644 (file)
--- a/riscv/insns/div_d.h
+++ b/riscv/insns/div_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_div(FRA, FRB);
+FRDR = f64_div(FRS1, FRS2);
 set_fp_exceptions;